Signal processing architectures

Signal processing architectures for SoC ICs
Kezdés éve: 
Befejezés éve: 
Assoc. Prof. F.C.M. Lau, Dept. of Electronic and Information Eng., The Hong Kong Polytechnic University, Prof. C.K. Tse, Dept. of Electronic and Information Eng., The Hong Kong Polytechnic University, Prof. G. Chen, Director, Centre for Chaos Control and Synchronization, City University of Hong Kong

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By today, the design of integrated circuits (ICs) has become an independent field of engineering which is separated from the IC production. The latest complex IC-s have been developed using the system-on-a-chip (SoC) concept which means that a entire system, for example a complete Blue Tooth receiver, is implemented on a single chip. To reduce the development cost and time, circuits developed previously for another application are reused frequently as IP blocks (intellectual property). The most important blocks of these complex ICs are the mixed-signal processing circuits, where analog, discrete-time and digital signal processing is performed in an inseparable manner. The research project will develop a systematic design method for the mixed-signal circuits, especially for the sampling and charge-pump phase-locked loops. The theory of system level analysis and computer simulation of complex SoC ICs will be established. The method to be developed will be able to include IP blocks available on the market. The main goals of the research program are as follows: Development of design and analysis methods for the mixed-signal processing circuit. Our main goal is to elaborate baseband models and design equations for the sampling and charge-pump phase-locked loops used widely in frequency synthesis. The new signal processing architectures developed for the system-on-a-chip concept and which may use IP blocks will be analyzed and compared. The main goals are to find systematic design methods and new signal processing algorithms. We are going to find methods for the ultra fast simulation of the SoC integrated circuits. Our goal is to develop an algorithm which is suitable for the simulation of complex ICs and which can use IP blocks available on the market into the system under simulation.

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