Project Status (01/14/2014 - 00:45:20)
Project File: system.xmp Implementation State: Programming File Generated
Module Name: system
  • Errors:
No Errors
Product Version:EDK 14.7
  • Warnings:
71 Warnings (0 new)
 
XPS Reports [-]
Report NameGenerated ErrorsWarningsInfos
Platgen Log FileCs jan. 2 00:00:29 201403 Warnings (1 new)26 Infos (0 new)
Simgen Log File    
BitInit Log File    
System Log FileP jan. 10 21:54:29 2014   
 
XPS Synthesis Summary (estimated values) [-]
ReportGeneratedFlip Flops UsedLUTs UsedBRAMS UsedErrors
systemCs jan. 2 00:00:47 201449735751280
system_logsys_axi_sp6_simpleio_0_wrapperCs jan. 2 00:00:25 2014202197 0
system_logsys_axi_spi_if_0_wrapperCs jan. 2 00:00:19 2014177267 0
system_logsys_axi_eth_if_0_wrapperCs jan. 2 00:00:11 2014136130 0
system_sdram_wrapperCs jan. 2 00:00:05 2014222477 0
system_clock_generator_0_wrapperSze jan. 1 23:59:58 2014 1 0
system_axi4_0_wrapperSze jan. 1 04:15:49 2014286310 0
system_rs232_wrapperSze jan. 1 04:15:41 201485106 0
system_axi4lite_0_wrapperSze jan. 1 04:15:35 2014150346 0
system_axi_timer_0_wrapperSze jan. 1 04:15:27 2014222321 0
system_debug_module_wrapperSze jan. 1 04:15:15 20146949 0
system_microblaze_0_wrapperSze jan. 1 04:15:10 201432633337120
system_microblaze_0_bram_block_wrapperSze jan. 1 04:14:32 2014  160
system_microblaze_0_d_bram_ctrl_wrapperSze jan. 1 04:14:26 201426 0
system_microblaze_0_dlmb_wrapperSze jan. 1 04:14:21 20141  0
system_microblaze_0_i_bram_ctrl_wrapperSze jan. 1 04:14:17 201426 0
system_microblaze_0_ilmb_wrapperSze jan. 1 04:14:12 20141  0
system_microblaze_0_intc_wrapperSze jan. 1 04:14:07 201486144 0
system_proc_sys_reset_0_wrapperSze jan. 1 04:14:01 20146954 0
 
Device Utilization Summary (actual values) [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 3,904 11,440 34%  
    Number used as Flip Flops 3,893      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 11      
Number of Slice LUTs 4,701 5,720 82%  
    Number used as logic 4,224 5,720 73%  
        Number using O6 output only 3,051      
        Number using O5 output only 109      
        Number using O5 and O6 1,064      
        Number used as ROM 0      
    Number used as Memory 269 1,440 18%  
        Number used as Dual Port RAM 88      
            Number using O6 output only 0      
            Number using O5 output only 4      
            Number using O5 and O6 84      
        Number used as Single Port RAM 7      
            Number using O6 output only 0      
            Number using O5 output only 1      
            Number using O5 and O6 6      
        Number used as Shift Register 174      
            Number using O6 output only 53      
            Number using O5 output only 11      
            Number using O5 and O6 110      
    Number used exclusively as route-thrus 208      
        Number with same-slice register load 180      
        Number with same-slice carry load 4      
        Number with other load 24      
Number of occupied Slices 1,419 1,430 99%  
Number of MUXCYs used 748 2,860 26%  
Number of LUT Flip Flop pairs used 5,122      
    Number with an unused Flip Flop 1,676 5,122 32%  
    Number with an unused LUT 421 5,122 8%  
    Number of fully used LUT-FF pairs 3,025 5,122 59%  
    Number of unique control sets 269      
    Number of slice register sites lost
        to control set restrictions
1,078 11,440 9%  
Number of bonded IOBs 86 102 84%  
    Number of LOCed IOBs 86 86 100%  
    IOB Flip Flops 155      
Number of RAMB16BWERs 28 32 87%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 44 200 22%  
    Number used as ILOGIC2s 44      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 16 200 8%  
    Number used as IODELAY2s 16      
    Number used as IODRP2s 0      
    Number used as IODRP2_MCBs 0      
Number of OLOGIC2/OSERDES2s 74 200 37%  
    Number used as OLOGIC2s 74      
    Number used as OSERDES2s 0      
Number of BSCANs 1 4 25%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 5 16 31%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.07      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Translation ReportCurrentP jan. 10 21:37:16 201406 Warnings (0 new)2 Infos (0 new)
Map ReportCurrentP jan. 10 21:39:20 2014021 Warnings (0 new)664 Infos (0 new)
Place and Route ReportCurrentP jan. 10 21:40:33 2014023 Warnings (0 new)2 Infos (0 new)
Post-PAR Static Timing ReportCurrentP jan. 10 21:40:44 2014004 Infos (0 new)
Bitgen ReportCurrentP jan. 10 21:41:08 2014021 Warnings (0 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentP jan. 10 21:41:08 2014
WebTalk Log FileCurrentP jan. 10 21:41:16 2014

Date Generated: 01/14/2014 - 00:45:20