| Environment Settings | ||||
| Environment Variable | xst | ngdbuild | map | par |
| PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
< data not available > | < data not available > | < data not available > |
| Path | C:\Xilinx\14.6\ISE_DS\ISE\\lib\nt; C:\Xilinx\14.6\ISE_DS\ISE\\bin\nt; C:\Xilinx\14.6\ISE_DS\ISE\bin\nt; C:\Xilinx\14.6\ISE_DS\ISE\lib\nt; C:\Xilinx\14.6\ISE_DS\ISE\..\..\..\DocNav; C:\Xilinx\14.6\ISE_DS\PlanAhead\bin; C:\Xilinx\14.6\ISE_DS\EDK\bin\nt; C:\Xilinx\14.6\ISE_DS\EDK\lib\nt; C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\nt\bin; C:\Xilinx\14.6\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; C:\Xilinx\14.6\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\14.6\ISE_DS\EDK\gnu\arm\nt\bin; C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin; C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin; C:\Xilinx\14.6\ISE_DS\common\bin\nt; C:\Xilinx\14.6\ISE_DS\common\lib\nt; C:\MentorGraphics\PADS\9.5PADS\SDD_HOME\common\win32\bin; C:\MentorGraphics\PADS\9.5PADS\SDD_HOME\common\win32\lib; C:\MentorGraphics\PADS\9.5PADS\MGC_HOME.ixn\bin; C:\MentorGraphics\PADS\9.5PADS\MGC_HOME.ixn\lib; C:\Nvidia\CUDA Toolkit\bin; C:\Nvidia\CUDA Toolkit\libnvvp; C:\Program Files\NVIDIA Corporation\PhysX\Common; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Windows Kits\8.0\Windows Performance Toolkit\; C:\Program Files\Microsoft SQL Server\110\Tools\Binn\; C:\MATLAB\R2012a\runtime\win32; C:\MATLAB\R2012a\bin; C:\MentorGraphics\PADS\9.5PADS\SDD_HOME\CAMCAD |
< data not available > | < data not available > | < data not available > |
| XILINX | C:\Xilinx\14.6\ISE_DS\ISE\ | < data not available > | < data not available > | < data not available > |
| XILINXD_LICENSE_FILE | 2100@fbpc36.mit.bme.hu | < data not available > | < data not available > | < data not available > |
| XILINX_DSP | C:\Xilinx\14.6\ISE_DS\ISE | < data not available > | < data not available > | < data not available > |
| XILINX_EDK | C:\Xilinx\14.6\ISE_DS\EDK | < data not available > | < data not available > | < data not available > |
| XILINX_PLANAHEAD | C:\Xilinx\14.6\ISE_DS\PlanAhead | < data not available > | < data not available > | < data not available > |
| Synthesis Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ifn | ledsw.prj | ||
| -ifmt | mixed | MIXED | |
| -ofn | ledsw | ||
| -ofmt | NGC | NGC | |
| -p | xc3s250e-4-tq144 | ||
| -top | ledsw | ||
| -opt_mode | Optimization Goal | Speed | SPEED |
| -opt_level | Optimization Effort | 1 | 1 |
| -iuc | Use synthesis Constraints File | NO | NO |
| -keep_hierarchy | Keep Hierarchy | No | NO |
| -netlist_hierarchy | Netlist Hierarchy | As_Optimized | as_optimized |
| -rtlview | Generate RTL Schematic | Yes | NO |
| -glob_opt | Global Optimization Goal | AllClockNets | ALLCLOCKNETS |
| -read_cores | Read Cores | YES | YES |
| -write_timing_constraints | Write Timing Constraints | NO | NO |
| -cross_clock_analysis | Cross Clock Analysis | NO | NO |
| -bus_delimiter | Bus Delimiter | <> | <> |
| -slice_utilization_ratio | Slice Utilization Ratio | 100 | 100% |
| -bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100% |
| -verilog2001 | Verilog 2001 | YES | YES |
| -fsm_extract | YES | YES | |
| -fsm_encoding | Auto | AUTO | |
| -safe_implementation | No | NO | |
| -fsm_style | LUT | LUT | |
| -ram_extract | Yes | YES | |
| -ram_style | Auto | AUTO | |
| -rom_extract | Yes | YES | |
| -shreg_extract | YES | YES | |
| -rom_style | Auto | AUTO | |
| -auto_bram_packing | NO | NO | |
| -resource_sharing | YES | YES | |
| -async_to_sync | NO | NO | |
| -mult_style | Auto | AUTO | |
| -iobuf | YES | YES | |
| -max_fanout | 100000 | 500 | |
| -bufg | 24 | 24 | |
| -register_duplication | YES | YES | |
| -register_balancing | No | NO | |
| -optimize_primitives | NO | NO | |
| -use_clock_enable | Yes | YES | |
| -use_sync_set | Yes | YES | |
| -use_sync_reset | Yes | YES | |
| -iob | Auto | AUTO | |
| -equivalent_register_removal | YES | YES | |
| -slice_utilization_ratio_maxmargin | 5 | 0% | |
| Operating System Information | ||||
| Operating System Information | xst | ngdbuild | map | par |
| CPU Architecture/Speed | Intel(R) Core(TM)2 CPU 4400 @ 2.00GHz/1998 MHz | < data not available > | < data not available > | < data not available > |
| Host | FPGA03 | < data not available > | < data not available > | < data not available > |
| OS Name | Microsoft Windows 7 , 32-bit | < data not available > | < data not available > | < data not available > |
| OS Release | Service Pack 1 (build 7601) | < data not available > | < data not available > | < data not available > |