Resources Used |
1 |
MicroBlaze |
1 |
Processor Local Bus (PLB) 4.6 |
2 |
Local Memory Bus (LMB) 1.0 |
1 |
Block RAM (BRAM) Block |
2 |
LMB BRAM Controller |
1 |
LOGSYS_XCL_SDRAM_CTRL |
1 |
XPS Timer/Counter |
1 |
XPS UART (Lite) |
1 |
Clock Generator |
1 |
MicroBlaze Debug Module (MDM) |
1 |
Processor System Reset Module |
1 |
XPS Interrupt Controller |
1 |
LOGSYS_PLB_ETH_IF |
1 |
LOGSYS_PLB_SPI_IF |
1 |
LOGSYS_PLB_SP6_SIMPLEIO |
|
Specifics |
Generated |
Sat Jan 11 02:09:10 2014 |
EDK Version |
14.7 |
Device Family |
spartan6 |
Device |
xc6slx9tqg144-2 |
|
|
|
These are the external ports defined in the MHS file.
|
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK indicates Clock ports, (SIGIS = CLK) INTR indicates Interrupt ports,(SIGIS = INTR) RESET indicates Reset ports, (SIGIS = RST) BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
|
# |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
SHARED
|
man_rstn |
I |
1 |
sys_rst_s |
RESET |
RS232
|
dev_mosi |
I |
1 |
fpga_0_RS232_RX_pin |
|
RS232
|
dev_miso |
O |
1 |
fpga_0_RS232_TX_pin |
|
SDRAM
|
SDRAM_mem_data_pin |
IO |
0:15 |
SDRAM_mem_data |
|
SDRAM
|
SDRAM_mem_addr_pin |
O |
0:17 |
SDRAM_mem_addr |
|
SDRAM
|
SDRAM_mem_lbn_pin |
O |
1 |
SDRAM_mem_lbn |
|
SDRAM
|
SDRAM_mem_ubn_pin |
O |
1 |
SDRAM_mem_ubn |
|
SDRAM
|
SDRAM_mem_wen_pin |
O |
1 |
SDRAM_mem_wen |
|
SDRAM
|
SDRAM_sdram_cke_pin |
O |
1 |
SDRAM_sdram_cke |
|
SDRAM
|
SDRAM_sdram_clk_pin |
O |
1 |
SDRAM_sdram_clk |
|
SDRAM
|
SDRAM_sdram_csn_pin |
O |
1 |
SDRAM_sdram_csn |
|
SDRAM
|
SDRAM_sram_csn_pin |
O |
1 |
SDRAM_sram_csn |
|
SDRAM
|
SDRAM_sram_oen_pin |
O |
1 |
SDRAM_sram_oen |
|
clock_generator_0
|
osc_clk |
I |
1 |
CLK_S |
CLK |
logsys_plb_eth_if_0
|
eth_irq |
I |
1 |
logsys_plb_eth_if_0_eth_irq |
|
logsys_plb_eth_if_0
|
eth_ad |
IO |
0:7 |
logsys_plb_eth_if_0_eth_ad |
|
logsys_plb_eth_if_0
|
eth_al |
O |
1 |
logsys_plb_eth_if_0_eth_al |
|
logsys_plb_eth_if_0
|
eth_en |
O |
1 |
logsys_plb_eth_if_0_eth_en |
|
logsys_plb_eth_if_0
|
eth_rnw_ad8 |
O |
1 |
logsys_plb_eth_if_0_eth_rnw_ad8 |
|
logsys_plb_sp6_simpleio_0
|
btn_in |
I |
0:2 |
net_btn_in |
|
logsys_plb_sp6_simpleio_0
|
cpld_miso |
I |
1 |
logsys_plb_sp6_simpleio_0_cpld_miso |
|
logsys_plb_sp6_simpleio_0
|
gpio_io |
IO |
0:12 |
logsys_plb_sp6_simpleio_0_gpio_IO |
|
logsys_plb_sp6_simpleio_0
|
cpld_clk |
O |
1 |
logsys_plb_sp6_simpleio_0_cpld_clk |
|
logsys_plb_sp6_simpleio_0
|
cpld_jtagen |
O |
1 |
logsys_plb_sp6_simpleio_0_cpld_jtagen |
|
logsys_plb_sp6_simpleio_0
|
cpld_load |
O |
1 |
logsys_plb_sp6_simpleio_0_cpld_load |
|
logsys_plb_sp6_simpleio_0
|
cpld_mosi |
O |
1 |
logsys_plb_sp6_simpleio_0_cpld_mosi |
|
logsys_plb_sp6_simpleio_0
|
cpld_rstn |
O |
1 |
logsys_plb_sp6_simpleio_0_cpld_rstn |
|
logsys_plb_spi_if_0
|
spi_miso |
IO |
1 |
logsys_plb_spi_if_0_spi_miso |
|
logsys_plb_spi_if_0
|
spi_clk |
O |
1 |
logsys_plb_spi_if_0_spi_clk |
|
logsys_plb_spi_if_0
|
spi_flash_csn |
O |
1 |
logsys_plb_spi_if_0_flash_csn |
|
logsys_plb_spi_if_0
|
spi_lcd_csn |
O |
1 |
logsys_plb_spi_if_0_lcd_csn |
|
logsys_plb_spi_if_0
|
spi_mosi |
O |
1 |
logsys_plb_spi_if_0_spi_mosi |
|
logsys_plb_spi_if_0
|
spi_sdcard_csn |
O |
1 |
logsys_plb_spi_if_0_sdcard_csn |
|
|
|
microblaze_0
MicroBlaze The MicroBlaze 32 bit soft processor
|
IP Specs |
Core |
Version |
Documentation |
microblaze |
8.50.c |
IP |
|
 |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_SCO |
0 |
C_FREQ |
0 |
C_DATA_SIZE |
32 |
C_DYNAMIC_BUS_SIZING |
1 |
C_FAMILY |
virtex5 |
C_INSTANCE |
microblaze |
C_AVOID_PRIMITIVES |
0 |
C_FAULT_TOLERANT |
0 |
C_ECC_USE_CE_EXCEPTION |
0 |
C_LOCKSTEP_SLAVE |
0 |
C_ENDIANNESS |
0 |
C_AREA_OPTIMIZED |
0 |
C_OPTIMIZATION |
0 |
C_INTERCONNECT |
1 |
C_STREAM_INTERCONNECT |
0 |
C_BASE_VECTORS |
0x00000000 |
C_DPLB_DWIDTH |
32 |
C_DPLB_NATIVE_DWIDTH |
32 |
C_DPLB_BURST_EN |
0 |
C_DPLB_P2P |
0 |
C_IPLB_DWIDTH |
32 |
C_IPLB_NATIVE_DWIDTH |
32 |
C_IPLB_BURST_EN |
0 |
C_IPLB_P2P |
0 |
C_M_AXI_DP_SUPPORTS_THREADS |
0 |
C_M_AXI_DP_THREAD_ID_WIDTH |
1 |
C_M_AXI_DP_SUPPORTS_READ |
1 |
C_M_AXI_DP_SUPPORTS_WRITE |
1 |
C_M_AXI_DP_SUPPORTS_NARROW_BURST |
0 |
C_M_AXI_DP_DATA_WIDTH |
32 |
C_M_AXI_DP_ADDR_WIDTH |
32 |
C_M_AXI_DP_PROTOCOL |
AXI4LITE |
C_M_AXI_DP_EXCLUSIVE_ACCESS |
0 |
C_INTERCONNECT_M_AXI_DP_READ_ISSUING |
1 |
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING |
1 |
C_M_AXI_IP_SUPPORTS_THREADS |
0 |
C_M_AXI_IP_THREAD_ID_WIDTH |
1 |
C_M_AXI_IP_SUPPORTS_READ |
1 |
C_M_AXI_IP_SUPPORTS_WRITE |
0 |
C_M_AXI_IP_SUPPORTS_NARROW_BURST |
0 |
C_M_AXI_IP_DATA_WIDTH |
32 |
C_M_AXI_IP_ADDR_WIDTH |
32 |
C_M_AXI_IP_PROTOCOL |
AXI4LITE |
C_INTERCONNECT_M_AXI_IP_READ_ISSUING |
1 |
C_D_AXI |
0 |
C_D_PLB |
0 |
C_D_LMB |
1 |
C_I_AXI |
0 |
C_I_PLB |
0 |
C_I_LMB |
1 |
C_USE_MSR_INSTR |
1 |
C_USE_PCMP_INSTR |
1 |
C_USE_BARREL |
1 |
C_USE_DIV |
1 |
C_USE_HW_MUL |
2 |
C_USE_FPU |
0 |
C_USE_REORDER_INSTR |
1 |
C_UNALIGNED_EXCEPTIONS |
0 |
C_ILL_OPCODE_EXCEPTION |
0 |
C_M_AXI_I_BUS_EXCEPTION |
0 |
C_M_AXI_D_BUS_EXCEPTION |
0 |
C_IPLB_BUS_EXCEPTION |
0 |
C_DPLB_BUS_EXCEPTION |
0 |
C_DIV_ZERO_EXCEPTION |
0 |
C_FPU_EXCEPTION |
0 |
C_FSL_EXCEPTION |
0 |
C_USE_STACK_PROTECTION |
0 |
C_PVR |
0 |
C_PVR_USER1 |
0x00 |
C_PVR_USER2 |
0x00000000 |
C_DEBUG_ENABLED |
1 |
C_NUMBER_OF_PC_BRK |
1 |
C_NUMBER_OF_RD_ADDR_BRK |
0 |
C_NUMBER_OF_WR_ADDR_BRK |
0 |
C_INTERRUPT_IS_EDGE |
0 |
C_EDGE_IS_POSITIVE |
1 |
C_RESET_MSR |
0x00000000 |
C_OPCODE_0x0_ILLEGAL |
0 |
C_FSL_LINKS |
0 |
C_FSL_DATA_SIZE |
32 |
C_USE_EXTENDED_FSL_INSTR |
0 |
C_M0_AXIS_PROTOCOL |
GENERIC |
C_S0_AXIS_PROTOCOL |
GENERIC |
C_M1_AXIS_PROTOCOL |
GENERIC |
C_S1_AXIS_PROTOCOL |
GENERIC |
C_M2_AXIS_PROTOCOL |
GENERIC |
C_S2_AXIS_PROTOCOL |
GENERIC |
C_M3_AXIS_PROTOCOL |
GENERIC |
C_S3_AXIS_PROTOCOL |
GENERIC |
C_M4_AXIS_PROTOCOL |
GENERIC |
C_S4_AXIS_PROTOCOL |
GENERIC |
C_M5_AXIS_PROTOCOL |
GENERIC |
C_S5_AXIS_PROTOCOL |
GENERIC |
C_M6_AXIS_PROTOCOL |
GENERIC |
C_S6_AXIS_PROTOCOL |
GENERIC |
C_M7_AXIS_PROTOCOL |
GENERIC |
C_S7_AXIS_PROTOCOL |
GENERIC |
C_M8_AXIS_PROTOCOL |
GENERIC |
C_S8_AXIS_PROTOCOL |
GENERIC |
C_M9_AXIS_PROTOCOL |
GENERIC |
C_S9_AXIS_PROTOCOL |
GENERIC |
C_M10_AXIS_PROTOCOL |
GENERIC |
C_S10_AXIS_PROTOCOL |
GENERIC |
C_M11_AXIS_PROTOCOL |
GENERIC |
C_S11_AXIS_PROTOCOL |
GENERIC |
C_M12_AXIS_PROTOCOL |
GENERIC |
C_S12_AXIS_PROTOCOL |
GENERIC |
C_M13_AXIS_PROTOCOL |
GENERIC |
C_S13_AXIS_PROTOCOL |
GENERIC |
C_M14_AXIS_PROTOCOL |
GENERIC |
|
|
Name |
Value |
C_S14_AXIS_PROTOCOL |
GENERIC |
C_M15_AXIS_PROTOCOL |
GENERIC |
C_S15_AXIS_PROTOCOL |
GENERIC |
C_M0_AXIS_DATA_WIDTH |
32 |
C_S0_AXIS_DATA_WIDTH |
32 |
C_M1_AXIS_DATA_WIDTH |
32 |
C_S1_AXIS_DATA_WIDTH |
32 |
C_M2_AXIS_DATA_WIDTH |
32 |
C_S2_AXIS_DATA_WIDTH |
32 |
C_M3_AXIS_DATA_WIDTH |
32 |
C_S3_AXIS_DATA_WIDTH |
32 |
C_M4_AXIS_DATA_WIDTH |
32 |
C_S4_AXIS_DATA_WIDTH |
32 |
C_M5_AXIS_DATA_WIDTH |
32 |
C_S5_AXIS_DATA_WIDTH |
32 |
C_M6_AXIS_DATA_WIDTH |
32 |
C_S6_AXIS_DATA_WIDTH |
32 |
C_M7_AXIS_DATA_WIDTH |
32 |
C_S7_AXIS_DATA_WIDTH |
32 |
C_M8_AXIS_DATA_WIDTH |
32 |
C_S8_AXIS_DATA_WIDTH |
32 |
C_M9_AXIS_DATA_WIDTH |
32 |
C_S9_AXIS_DATA_WIDTH |
32 |
C_M10_AXIS_DATA_WIDTH |
32 |
C_S10_AXIS_DATA_WIDTH |
32 |
C_M11_AXIS_DATA_WIDTH |
32 |
C_S11_AXIS_DATA_WIDTH |
32 |
C_M12_AXIS_DATA_WIDTH |
32 |
C_S12_AXIS_DATA_WIDTH |
32 |
C_M13_AXIS_DATA_WIDTH |
32 |
C_S13_AXIS_DATA_WIDTH |
32 |
C_M14_AXIS_DATA_WIDTH |
32 |
C_S14_AXIS_DATA_WIDTH |
32 |
C_M15_AXIS_DATA_WIDTH |
32 |
C_S15_AXIS_DATA_WIDTH |
32 |
C_ICACHE_BASEADDR |
0xC0000000 |
C_ICACHE_HIGHADDR |
0xC1FFFFFF |
C_USE_ICACHE |
1 |
C_ALLOW_ICACHE_WR |
1 |
C_ADDR_TAG_BITS |
17 |
C_CACHE_BYTE_SIZE |
8192 |
C_ICACHE_USE_FSL |
1 |
C_ICACHE_LINE_LEN |
8 |
C_ICACHE_ALWAYS_USED |
1 |
C_ICACHE_INTERFACE |
0 |
C_ICACHE_VICTIMS |
0 |
C_ICACHE_STREAMS |
0 |
C_ICACHE_FORCE_TAG_LUTRAM |
0 |
C_ICACHE_DATA_WIDTH |
0 |
C_M_AXI_IC_SUPPORTS_THREADS |
0 |
C_M_AXI_IC_THREAD_ID_WIDTH |
1 |
C_M_AXI_IC_SUPPORTS_READ |
1 |
C_M_AXI_IC_SUPPORTS_WRITE |
0 |
C_M_AXI_IC_SUPPORTS_NARROW_BURST |
0 |
C_M_AXI_IC_DATA_WIDTH |
32 |
C_M_AXI_IC_ADDR_WIDTH |
32 |
C_M_AXI_IC_PROTOCOL |
AXI4 |
C_M_AXI_IC_USER_VALUE |
0b11111 |
C_M_AXI_IC_SUPPORTS_USER_SIGNALS |
1 |
C_M_AXI_IC_AWUSER_WIDTH |
5 |
C_M_AXI_IC_ARUSER_WIDTH |
5 |
C_M_AXI_IC_WUSER_WIDTH |
1 |
C_M_AXI_IC_RUSER_WIDTH |
1 |
C_M_AXI_IC_BUSER_WIDTH |
1 |
C_INTERCONNECT_M_AXI_IC_READ_ISSUING |
2 |
C_DCACHE_BASEADDR |
0xC0000000 |
C_DCACHE_HIGHADDR |
0xC1FFFFFF |
C_USE_DCACHE |
1 |
C_ALLOW_DCACHE_WR |
1 |
C_DCACHE_ADDR_TAG |
17 |
C_DCACHE_BYTE_SIZE |
8192 |
C_DCACHE_USE_FSL |
1 |
C_DCACHE_LINE_LEN |
8 |
C_DCACHE_ALWAYS_USED |
1 |
C_DCACHE_INTERFACE |
0 |
C_DCACHE_USE_WRITEBACK |
0 |
C_DCACHE_VICTIMS |
0 |
C_DCACHE_FORCE_TAG_LUTRAM |
0 |
C_DCACHE_DATA_WIDTH |
0 |
C_M_AXI_DC_SUPPORTS_THREADS |
0 |
C_M_AXI_DC_THREAD_ID_WIDTH |
1 |
C_M_AXI_DC_SUPPORTS_READ |
1 |
C_M_AXI_DC_SUPPORTS_WRITE |
1 |
C_M_AXI_DC_SUPPORTS_NARROW_BURST |
0 |
C_M_AXI_DC_DATA_WIDTH |
32 |
C_M_AXI_DC_ADDR_WIDTH |
32 |
C_M_AXI_DC_PROTOCOL |
AXI4 |
C_M_AXI_DC_EXCLUSIVE_ACCESS |
0 |
C_M_AXI_DC_USER_VALUE |
0b11111 |
C_M_AXI_DC_SUPPORTS_USER_SIGNALS |
1 |
C_M_AXI_DC_AWUSER_WIDTH |
5 |
C_M_AXI_DC_ARUSER_WIDTH |
5 |
C_M_AXI_DC_WUSER_WIDTH |
1 |
C_M_AXI_DC_RUSER_WIDTH |
1 |
C_M_AXI_DC_BUSER_WIDTH |
1 |
C_INTERCONNECT_M_AXI_DC_READ_ISSUING |
2 |
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING |
32 |
C_USE_MMU |
3 |
C_MMU_DTLB_SIZE |
4 |
C_MMU_ITLB_SIZE |
2 |
C_MMU_TLB_ACCESS |
3 |
C_MMU_ZONES |
2 |
C_MMU_PRIVILEGED_INSTR |
0 |
C_USE_INTERRUPT |
0 |
C_USE_EXT_BRK |
0 |
C_USE_EXT_NM_BRK |
0 |
C_USE_BRANCH_TARGET_CACHE |
0 |
C_BRANCH_TARGET_CACHE_SIZE |
0 |
C_PC_WIDTH |
32 |
|
|
|
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
|
|
|
|
mdm_0
MicroBlaze Debug Module (MDM) Debug module for MicroBlaze Soft Processor.
|
IP Specs |
Core |
Version |
Documentation |
mdm |
2.10.a |
IP |
|
 |
PORT LIST |
These are the ports listed in the MHS file.
Please refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[LSB:MSB] |
SIGNAL |
0 |
Debug_SYS_Rst |
O |
1 |
Debug_SYS_Rst |
Bus Interfaces |
NAME |
TYPE |
BUSSTD |
BUS |
Connected To |
MBDEBUG_0 |
INITIATOR |
XIL_MBDEBUG3 |
microblaze_0_mdm_bus |
microblaze_0 |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_FAMILY |
virtex6 |
C_JTAG_CHAIN |
2 |
C_INTERCONNECT |
1 |
C_BASEADDR |
0xFFFFFFFF |
C_HIGHADDR |
0x00000000 |
C_SPLB_AWIDTH |
32 |
C_SPLB_DWIDTH |
32 |
C_SPLB_P2P |
0 |
C_SPLB_MID_WIDTH |
3 |
|
|
Name |
Value |
C_SPLB_NUM_MASTERS |
8 |
C_SPLB_NATIVE_DWIDTH |
32 |
C_SPLB_SUPPORT_BURSTS |
0 |
C_MB_DBG_PORTS |
1 |
C_USE_UART |
0 |
C_USE_BSCAN |
0 |
C_S_AXI_ADDR_WIDTH |
32 |
C_S_AXI_DATA_WIDTH |
32 |
C_S_AXI_PROTOCOL |
AXI4LITE |
|
|
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
|
|
|
|
Interrupt Controllers |
TOC |
xps_intc_0
XPS Interrupt Controller intc core attached to the PLBV46
|
IP Specs |
Core |
Version |
Documentation |
xps_intc |
2.01.a |
IP |
|
 |
PORT LIST |
These are the ports listed in the MHS file.
Please refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[LSB:MSB] |
SIGNAL |
0 |
Intr |
I |
1 |
logsys_plb_sp6_simpleio_0_irq & RS232_Interrupt & logsys_plb_spi_if_0_irq & logsys_plb_eth_if_0_interrupt & xps_timer_0_Interrupt |
1 |
Irq |
O |
1 |
microblaze_0_Interrupt |
Bus Interfaces |
NAME |
TYPE |
BUSSTD |
BUS |
Connected To |
SPLB |
SLAVE |
PLBV46 |
mb_plb |
6 Peripherals. |
Interrupt Priorities |
Priority |
SIG |
MODULE |
0 |
logsys_plb_sp6_simpleio_0_irq |
logsys_plb_sp6_simpleio_0 |
1 |
RS232_Interrupt |
RS232 |
2 |
logsys_plb_spi_if_0_irq |
logsys_plb_spi_if_0 |
3 |
logsys_plb_eth_if_0_interrupt |
logsys_plb_eth_if_0 |
4 |
xps_timer_0_Interrupt |
xps_timer_0 |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_FAMILY |
virtex5 |
C_BASEADDR |
0x80000000 |
C_HIGHADDR |
0x8000FFFF |
C_SPLB_AWIDTH |
32 |
C_SPLB_DWIDTH |
32 |
C_SPLB_P2P |
0 |
C_SPLB_NUM_MASTERS |
1 |
C_SPLB_MID_WIDTH |
1 |
C_SPLB_NATIVE_DWIDTH |
32 |
C_SPLB_SUPPORT_BURSTS |
0 |
|
|
Name |
Value |
C_NUM_INTR_INPUTS |
2 |
C_KIND_OF_INTR |
0xFFFFFFFF |
C_KIND_OF_EDGE |
0xFFFFFFFF |
C_KIND_OF_LVL |
0xFFFFFFFF |
C_HAS_IPR |
1 |
C_HAS_SIE |
1 |
C_HAS_CIE |
1 |
C_HAS_IVR |
1 |
C_IRQ_IS_LEVEL |
1 |
C_IRQ_ACTIVE |
1 |
|
|
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
|
|
|
|
dlmb
Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
|
IP Specs |
Core |
Version |
Documentation |
lmb_v10 |
2.00.b |
IP |
|
 |
PORT LIST |
These are the ports listed in the MHS file.
Please refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[LSB:MSB] |
SIGNAL |
0 |
LMB_Clk |
I |
1 |
clk_50_0000MHz |
1 |
SYS_Rst |
I |
1 |
sys_bus_reset |
Bus Connections |
INSTANCE |
INTERFACE TYPE |
INTERFACE NAME |
microblaze_0 |
MASTER |
DLMB |
dlmb_cntlr |
SLAVE |
SLMB |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_LMB_NUM_SLAVES |
4 |
C_LMB_AWIDTH |
32 |
C_LMB_DWIDTH |
32 |
C_EXT_RESET_HIGH |
1 |
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
|
|
|
ilmb
Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
|
IP Specs |
Core |
Version |
Documentation |
lmb_v10 |
2.00.b |
IP |
|
 |
PORT LIST |
These are the ports listed in the MHS file.
Please refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[LSB:MSB] |
SIGNAL |
0 |
LMB_Clk |
I |
1 |
clk_50_0000MHz |
1 |
SYS_Rst |
I |
1 |
sys_bus_reset |
Bus Connections |
INSTANCE |
INTERFACE TYPE |
INTERFACE NAME |
microblaze_0 |
MASTER |
ILMB |
ilmb_cntlr |
SLAVE |
SLMB |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_LMB_NUM_SLAVES |
4 |
C_LMB_AWIDTH |
32 |
C_LMB_DWIDTH |
32 |
C_EXT_RESET_HIGH |
1 |
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
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mb_plb
Processor Local Bus (PLB) 4.6 'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'
|
IP Specs |
Core |
Version |
Documentation |
plb_v46 |
1.05.a |
IP |
|
 |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_PLBV46_NUM_MASTERS |
4 |
C_PLBV46_NUM_SLAVES |
8 |
C_PLBV46_MID_WIDTH |
2 |
C_PLBV46_AWIDTH |
32 |
C_PLBV46_DWIDTH |
64 |
C_DCR_INTFCE |
0 |
C_BASEADDR |
0B1111111111 |
C_HIGHADDR |
0B0000000000 |
C_DCR_AWIDTH |
10 |
|
|
Name |
Value |
C_DCR_DWIDTH |
32 |
C_EXT_RESET_HIGH |
1 |
C_IRQ_ACTIVE |
1 |
C_NUM_CLK_PLB2OPB_REARB |
5 |
C_ADDR_PIPELINING_TYPE |
1 |
C_FAMILY |
virtex5 |
C_P2P |
0 |
C_ARB_TYPE |
0 |
|
|
|
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
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lmb_bram
Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.
|
IP Specs |
Core |
Version |
Documentation |
bram_block |
1.00.a |
IP |
|
 |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_MEMSIZE |
2048 |
C_PORT_DWIDTH |
32 |
C_PORT_AWIDTH |
32 |
C_NUM_WE |
4 |
C_FAMILY |
virtex2 |
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
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SDRAM
LOGSYS_XCL_SDRAM_CTRL XCL SDRAM controller for the LOGSYS Spartan-6 FPGA board.
|
IP Specs |
Core |
Version |
logsys_xcl_sdram_ctrl |
1.00.a |
|
 |
PORT LIST |
These are the ports listed in the MHS file.
|
# |
NAME |
DIR |
[LSB:MSB] |
SIGNAL |
0 |
rst |
I |
1 |
sys_bus_reset |
1 |
clk |
I |
1 |
clk_50_0000MHz |
2 |
clk2x |
I |
1 |
clock_generator_0_CLKOUT1 |
3 |
mem_addr |
O |
1 |
SDRAM_mem_addr |
4 |
mem_data |
IO |
1 |
SDRAM_mem_data |
5 |
mem_wen |
O |
1 |
SDRAM_mem_wen |
6 |
mem_lbn |
O |
1 |
SDRAM_mem_lbn |
7 |
mem_ubn |
O |
1 |
SDRAM_mem_ubn |
8 |
sram_csn |
O |
1 |
SDRAM_sram_csn |
9 |
sram_oen |
O |
1 |
SDRAM_sram_oen |
10 |
sdram_clk |
O |
1 |
SDRAM_sdram_clk |
11 |
sdram_cke |
O |
1 |
SDRAM_sdram_cke |
12 |
sdram_csn |
O |
1 |
SDRAM_sdram_csn |
Bus Interfaces |
NAME |
TYPE |
BUSSTD |
BUS |
Connected To |
XCL0 |
TARGET |
XIL_MEMORY_CHANNEL |
microblaze_0_IXCL |
microblaze_0 |
XCL1 |
TARGET |
XIL_MEMORY_CHANNEL |
microblaze_0_DXCL |
microblaze_0 |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_SYSCLK_PERIOD_PS |
10000 |
C_MEM_BASEADDR |
0xC0000000 |
C_MEM_HIGHADDR |
0xC1FFFFFF |
C_XCL0_LINESIZE |
8 |
C_XCL1_LINESIZE |
8 |
C_T_SDRAM_RP_NS |
20 |
C_T_SDRAM_RFC_NS |
66 |
C_T_SDRAM_RMD_CLK |
2 |
|
|
Name |
Value |
C_T_SDRAM_RCD_NS |
20 |
C_T_SDRAM_RC_NS |
66 |
C_T_SDRAM_RAS_MIN_NS |
42 |
C_T_SDRAM_RAS_MAX_NS |
100000 |
C_T_SDRAM_REFRESH_MS |
64 |
C_SDRAM_REFRESH_BURST |
8 |
C_SDRAM_CAS_LATENCY |
2 |
|
|
|
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
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dlmb_cntlr
LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus
|
IP Specs |
Core |
Version |
Documentation |
lmb_bram_if_cntlr |
3.10.c |
IP |
|
 |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_BASEADDR |
0x00000000 |
C_HIGHADDR |
0x00007FFF |
C_FAMILY |
virtex5 |
C_MASK |
0x00800000 |
C_MASK1 |
0x00800000 |
C_MASK2 |
0x00800000 |
C_MASK3 |
0x00800000 |
C_LMB_AWIDTH |
32 |
C_LMB_DWIDTH |
32 |
C_ECC |
0 |
C_INTERCONNECT |
0 |
C_FAULT_INJECT |
0 |
C_CE_FAILING_REGISTERS |
0 |
C_UE_FAILING_REGISTERS |
0 |
C_ECC_STATUS_REGISTERS |
0 |
C_ECC_ONOFF_REGISTER |
0 |
C_ECC_ONOFF_RESET_VALUE |
1 |
C_CE_COUNTER_WIDTH |
0 |
|
|
Name |
Value |
C_WRITE_ACCESS |
2 |
C_NUM_LMB |
1 |
C_SPLB_CTRL_BASEADDR |
0xFFFFFFFF |
C_SPLB_CTRL_HIGHADDR |
0x00000000 |
C_SPLB_CTRL_AWIDTH |
32 |
C_SPLB_CTRL_DWIDTH |
32 |
C_SPLB_CTRL_P2P |
0 |
C_SPLB_CTRL_MID_WIDTH |
1 |
C_SPLB_CTRL_NUM_MASTERS |
1 |
C_SPLB_CTRL_SUPPORT_BURSTS |
0 |
C_SPLB_CTRL_NATIVE_DWIDTH |
32 |
C_SPLB_CTRL_CLK_FREQ_HZ |
100000000 |
C_S_AXI_CTRL_ACLK_FREQ_HZ |
100000000 |
C_S_AXI_CTRL_BASEADDR |
0xFFFFFFFF |
C_S_AXI_CTRL_HIGHADDR |
0x00000000 |
C_S_AXI_CTRL_ADDR_WIDTH |
32 |
C_S_AXI_CTRL_DATA_WIDTH |
32 |
C_S_AXI_CTRL_PROTOCOL |
AXI4LITE |
|
|
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
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ilmb_cntlr
LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus
|
IP Specs |
Core |
Version |
Documentation |
lmb_bram_if_cntlr |
3.10.c |
IP |
|
 |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_BASEADDR |
0x00000000 |
C_HIGHADDR |
0x00007FFF |
C_FAMILY |
virtex5 |
C_MASK |
0x00800000 |
C_MASK1 |
0x00800000 |
C_MASK2 |
0x00800000 |
C_MASK3 |
0x00800000 |
C_LMB_AWIDTH |
32 |
C_LMB_DWIDTH |
32 |
C_ECC |
0 |
C_INTERCONNECT |
0 |
C_FAULT_INJECT |
0 |
C_CE_FAILING_REGISTERS |
0 |
C_UE_FAILING_REGISTERS |
0 |
C_ECC_STATUS_REGISTERS |
0 |
C_ECC_ONOFF_REGISTER |
0 |
C_ECC_ONOFF_RESET_VALUE |
1 |
C_CE_COUNTER_WIDTH |
0 |
|
|
Name |
Value |
C_WRITE_ACCESS |
2 |
C_NUM_LMB |
1 |
C_SPLB_CTRL_BASEADDR |
0xFFFFFFFF |
C_SPLB_CTRL_HIGHADDR |
0x00000000 |
C_SPLB_CTRL_AWIDTH |
32 |
C_SPLB_CTRL_DWIDTH |
32 |
C_SPLB_CTRL_P2P |
0 |
C_SPLB_CTRL_MID_WIDTH |
1 |
C_SPLB_CTRL_NUM_MASTERS |
1 |
C_SPLB_CTRL_SUPPORT_BURSTS |
0 |
C_SPLB_CTRL_NATIVE_DWIDTH |
32 |
C_SPLB_CTRL_CLK_FREQ_HZ |
100000000 |
C_S_AXI_CTRL_ACLK_FREQ_HZ |
100000000 |
C_S_AXI_CTRL_BASEADDR |
0xFFFFFFFF |
C_S_AXI_CTRL_HIGHADDR |
0x00000000 |
C_S_AXI_CTRL_ADDR_WIDTH |
32 |
C_S_AXI_CTRL_DATA_WIDTH |
32 |
C_S_AXI_CTRL_PROTOCOL |
AXI4LITE |
|
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Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
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RS232
XPS UART (Lite) Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.
|
IP Specs |
Core |
Version |
Documentation |
xps_uartlite |
1.02.a |
IP |
|
 |
PORT LIST |
These are the ports listed in the MHS file.
Please refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[LSB:MSB] |
SIGNAL |
0 |
RX |
I |
1 |
fpga_0_RS232_RX_pin |
1 |
TX |
O |
1 |
fpga_0_RS232_TX_pin |
2 |
Interrupt |
O |
1 |
RS232_Interrupt |
Bus Interfaces |
NAME |
TYPE |
BUSSTD |
BUS |
Connected To |
SPLB |
SLAVE |
PLBV46 |
mb_plb |
6 Peripherals. |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_FAMILY |
virtex5 |
C_SPLB_CLK_FREQ_HZ |
100000000 |
C_BASEADDR |
0x82000000 |
C_HIGHADDR |
0x8200FFFF |
C_SPLB_AWIDTH |
32 |
C_SPLB_DWIDTH |
32 |
C_SPLB_P2P |
0 |
C_SPLB_MID_WIDTH |
1 |
|
|
Name |
Value |
C_SPLB_NUM_MASTERS |
1 |
C_SPLB_SUPPORT_BURSTS |
0 |
C_SPLB_NATIVE_DWIDTH |
32 |
C_BAUDRATE |
115200 |
C_DATA_BITS |
8 |
C_USE_PARITY |
0 |
C_ODD_PARITY |
0 |
|
|
|
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
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logsys_plb_eth_if_0
LOGSYS_PLB_ETH_IF Interface peripheral for the LOGSYS 10/100 Ethernet module.
|
IP Specs |
Core |
Version |
logsys_plb_eth_if |
1.00.a |
|
 |
PORT LIST |
These are the ports listed in the MHS file.
|
# |
NAME |
DIR |
[LSB:MSB] |
SIGNAL |
0 |
eth_en |
O |
1 |
logsys_plb_eth_if_0_eth_en |
1 |
eth_al |
O |
1 |
logsys_plb_eth_if_0_eth_al |
2 |
eth_rnw_ad8 |
O |
1 |
logsys_plb_eth_if_0_eth_rnw_ad8 |
3 |
eth_ad |
IO |
1 |
logsys_plb_eth_if_0_eth_ad |
4 |
eth_irq |
I |
1 |
logsys_plb_eth_if_0_eth_irq |
5 |
interrupt |
O |
1 |
logsys_plb_eth_if_0_interrupt |
Bus Interfaces |
NAME |
TYPE |
BUSSTD |
BUS |
Connected To |
SPLB |
SLAVE |
PLBV46 |
mb_plb |
6 Peripherals. |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_SPLB_AWIDTH |
32 |
C_SPLB_DWIDTH |
128 |
C_SPLB_NUM_MASTERS |
8 |
C_SPLB_MID_WIDTH |
3 |
C_SPLB_NATIVE_DWIDTH |
32 |
C_SPLB_P2P |
0 |
C_SPLB_SUPPORT_BURSTS |
0 |
|
|
Name |
Value |
C_SPLB_SMALLEST_MASTER |
32 |
C_SPLB_CLK_PERIOD_PS |
10000 |
C_INCLUDE_DPHASE_TIMER |
0 |
C_FAMILY |
virtex6 |
C_MEM0_BASEADDR |
0x84000000 |
C_MEM0_HIGHADDR |
0x8400FFFF |
|
|
|
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
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logsys_plb_sp6_simpleio_0
LOGSYS_PLB_SP6_SIMPLEIO Interface peripheral for the simple I/O devices on the LOGSYS Spartan-6 FPGA board (LEDs, seven-segment displays, DIP switch, navigation switch, buttons and GPIO).
|
IP Specs |
Core |
Version |
logsys_plb_sp6_simpleio |
1.00.a |
|
 |
PORT LIST |
These are the ports listed in the MHS file.
|
# |
NAME |
DIR |
[LSB:MSB] |
SIGNAL |
0 |
irq |
O |
1 |
logsys_plb_sp6_simpleio_0_irq |
1 |
btn_in |
I |
1 |
net_btn_in |
2 |
cpld_jtagen |
O |
1 |
logsys_plb_sp6_simpleio_0_cpld_jtagen |
3 |
cpld_rstn |
O |
1 |
logsys_plb_sp6_simpleio_0_cpld_rstn |
4 |
cpld_clk |
O |
1 |
logsys_plb_sp6_simpleio_0_cpld_clk |
5 |
cpld_load |
O |
1 |
logsys_plb_sp6_simpleio_0_cpld_load |
6 |
cpld_mosi |
O |
1 |
logsys_plb_sp6_simpleio_0_cpld_mosi |
7 |
cpld_miso |
I |
1 |
logsys_plb_sp6_simpleio_0_cpld_miso |
8 |
gpio_IO |
IO |
1 |
logsys_plb_sp6_simpleio_0_gpio_IO |
Bus Interfaces |
NAME |
TYPE |
BUSSTD |
BUS |
Connected To |
SPLB |
SLAVE |
PLBV46 |
mb_plb |
6 Peripherals. |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_BASEADDR |
0x83000000 |
C_HIGHADDR |
0x8300FFFF |
C_SPLB_AWIDTH |
32 |
C_SPLB_DWIDTH |
128 |
C_SPLB_NUM_MASTERS |
8 |
C_SPLB_MID_WIDTH |
3 |
C_SPLB_NATIVE_DWIDTH |
32 |
C_SPLB_P2P |
0 |
|
|
Name |
Value |
C_SPLB_SUPPORT_BURSTS |
0 |
C_SPLB_SMALLEST_MASTER |
32 |
C_SPLB_CLK_PERIOD_PS |
10000 |
C_SPLB_CLK_FREQ_HZ |
100000000 |
C_INCLUDE_DPHASE_TIMER |
1 |
C_FAMILY |
virtex6 |
C_GPIO_ENABLE |
1 |
C_GPIO_WIDTH |
13 |
|
|
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
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logsys_plb_spi_if_0
LOGSYS_PLB_SPI_IF Master SPI peripheral for the LOGSYS Spartan-6 FPGA board.
|
IP Specs |
Core |
Version |
logsys_plb_spi_if |
1.00.a |
|
 |
PORT LIST |
These are the ports listed in the MHS file.
|
# |
NAME |
DIR |
[LSB:MSB] |
SIGNAL |
0 |
flash_csn |
O |
1 |
logsys_plb_spi_if_0_flash_csn |
1 |
lcd_csn |
O |
1 |
logsys_plb_spi_if_0_lcd_csn |
2 |
sdcard_csn |
O |
1 |
logsys_plb_spi_if_0_sdcard_csn |
3 |
spi_clk |
O |
1 |
logsys_plb_spi_if_0_spi_clk |
4 |
spi_mosi |
O |
1 |
logsys_plb_spi_if_0_spi_mosi |
5 |
spi_miso |
IO |
1 |
logsys_plb_spi_if_0_spi_miso |
6 |
irq |
O |
1 |
logsys_plb_spi_if_0_irq |
Bus Interfaces |
NAME |
TYPE |
BUSSTD |
BUS |
Connected To |
SPLB |
SLAVE |
PLBV46 |
mb_plb |
6 Peripherals. |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_BASEADDR |
0x85000000 |
C_HIGHADDR |
0x8500FFFF |
C_SPLB_AWIDTH |
32 |
C_SPLB_DWIDTH |
128 |
C_SPLB_NUM_MASTERS |
8 |
C_SPLB_MID_WIDTH |
3 |
C_SPLB_NATIVE_DWIDTH |
32 |
|
|
Name |
Value |
C_SPLB_P2P |
0 |
C_SPLB_SUPPORT_BURSTS |
0 |
C_SPLB_SMALLEST_MASTER |
32 |
C_SPLB_CLK_PERIOD_PS |
10000 |
C_INCLUDE_DPHASE_TIMER |
0 |
C_FAMILY |
virtex6 |
|
|
|
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
|
|
|
xps_timer_0
XPS Timer/Counter Timer counter with PLBV46 interface
|
IP Specs |
Core |
Version |
Documentation |
xps_timer |
1.02.a |
IP |
|
 |
PORT LIST |
These are the ports listed in the MHS file.
Please refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[LSB:MSB] |
SIGNAL |
0 |
Interrupt |
O |
1 |
xps_timer_0_Interrupt |
Bus Interfaces |
NAME |
TYPE |
BUSSTD |
BUS |
Connected To |
SPLB |
SLAVE |
PLBV46 |
mb_plb |
6 Peripherals. |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_FAMILY |
virtex5 |
C_COUNT_WIDTH |
32 |
C_ONE_TIMER_ONLY |
0 |
C_TRIG0_ASSERT |
1 |
C_TRIG1_ASSERT |
1 |
C_GEN0_ASSERT |
1 |
C_GEN1_ASSERT |
1 |
C_BASEADDR |
0x81000000 |
|
|
Name |
Value |
C_HIGHADDR |
0x8100FFFF |
C_SPLB_AWIDTH |
32 |
C_SPLB_DWIDTH |
32 |
C_SPLB_P2P |
0 |
C_SPLB_MID_WIDTH |
3 |
C_SPLB_NUM_MASTERS |
8 |
C_SPLB_SUPPORT_BURSTS |
0 |
C_SPLB_NATIVE_DWIDTH |
32 |
|
|
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
|
|
|
|
clock_generator_0
Clock Generator Clock generator for processor system.
|
IP Specs |
Core |
Version |
Documentation |
clock_generator |
4.03.a |
IP |
|
 |
PORT LIST |
These are the ports listed in the MHS file.
Please refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[LSB:MSB] |
SIGNAL |
0 |
CLKIN |
I |
1 |
CLK_S |
1 |
CLKOUT0 |
O |
1 |
clk_50_0000MHz |
2 |
RST |
I |
1 |
sys_rst_s |
3 |
LOCKED |
O |
1 |
Dcm_all_locked |
4 |
CLKOUT1 |
O |
1 |
clock_generator_0_CLKOUT1 |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_FAMILY |
virtex6 |
C_DEVICE |
NOT_SET |
C_PACKAGE |
NOT_SET |
C_SPEEDGRADE |
NOT_SET |
C_CLKIN_FREQ |
50000000 |
C_CLKOUT0_FREQ |
60000000 |
C_CLKOUT0_PHASE |
0 |
C_CLKOUT0_GROUP |
NONE |
C_CLKOUT0_BUF |
TRUE |
C_CLKOUT0_VARIABLE_PHASE |
FALSE |
C_CLKOUT1_FREQ |
120000000 |
C_CLKOUT1_PHASE |
0 |
C_CLKOUT1_GROUP |
NONE |
C_CLKOUT1_BUF |
TRUE |
C_CLKOUT1_VARIABLE_PHASE |
FALSE |
C_CLKOUT2_FREQ |
0 |
C_CLKOUT2_PHASE |
0 |
C_CLKOUT2_GROUP |
NONE |
C_CLKOUT2_BUF |
TRUE |
C_CLKOUT2_VARIABLE_PHASE |
FALSE |
C_CLKOUT3_FREQ |
0 |
C_CLKOUT3_PHASE |
0 |
C_CLKOUT3_GROUP |
NONE |
C_CLKOUT3_BUF |
TRUE |
C_CLKOUT3_VARIABLE_PHASE |
FALSE |
C_CLKOUT4_FREQ |
0 |
C_CLKOUT4_PHASE |
0 |
C_CLKOUT4_GROUP |
NONE |
C_CLKOUT4_BUF |
TRUE |
C_CLKOUT4_VARIABLE_PHASE |
FALSE |
C_CLKOUT5_FREQ |
0 |
C_CLKOUT5_PHASE |
0 |
C_CLKOUT5_GROUP |
NONE |
C_CLKOUT5_BUF |
TRUE |
C_CLKOUT5_VARIABLE_PHASE |
FALSE |
C_CLKOUT6_FREQ |
0 |
C_CLKOUT6_PHASE |
0 |
C_CLKOUT6_GROUP |
NONE |
C_CLKOUT6_BUF |
TRUE |
C_CLKOUT6_VARIABLE_PHASE |
FALSE |
C_CLKOUT7_FREQ |
0 |
C_CLKOUT7_PHASE |
0 |
C_CLKOUT7_GROUP |
NONE |
C_CLKOUT7_BUF |
TRUE |
C_CLKOUT7_VARIABLE_PHASE |
FALSE |
C_CLKOUT8_FREQ |
0 |
C_CLKOUT8_PHASE |
0 |
C_CLKOUT8_GROUP |
NONE |
C_CLKOUT8_BUF |
TRUE |
C_CLKOUT8_VARIABLE_PHASE |
FALSE |
C_CLKOUT9_FREQ |
0 |
C_CLKOUT9_PHASE |
0 |
C_CLKOUT9_GROUP |
NONE |
C_CLKOUT9_BUF |
TRUE |
C_CLKOUT9_VARIABLE_PHASE |
FALSE |
C_CLKOUT10_FREQ |
0 |
|
|
Name |
Value |
C_CLKOUT10_PHASE |
0 |
C_CLKOUT10_GROUP |
NONE |
C_CLKOUT10_BUF |
TRUE |
C_CLKOUT10_VARIABLE_PHASE |
FALSE |
C_CLKOUT11_FREQ |
0 |
C_CLKOUT11_PHASE |
0 |
C_CLKOUT11_GROUP |
NONE |
C_CLKOUT11_BUF |
TRUE |
C_CLKOUT11_VARIABLE_PHASE |
FALSE |
C_CLKOUT12_FREQ |
0 |
C_CLKOUT12_PHASE |
0 |
C_CLKOUT12_GROUP |
NONE |
C_CLKOUT12_BUF |
TRUE |
C_CLKOUT12_VARIABLE_PHASE |
FALSE |
C_CLKOUT13_FREQ |
0 |
C_CLKOUT13_PHASE |
0 |
C_CLKOUT13_GROUP |
NONE |
C_CLKOUT13_BUF |
TRUE |
C_CLKOUT13_VARIABLE_PHASE |
FALSE |
C_CLKOUT14_FREQ |
0 |
C_CLKOUT14_PHASE |
0 |
C_CLKOUT14_GROUP |
NONE |
C_CLKOUT14_BUF |
TRUE |
C_CLKOUT14_VARIABLE_PHASE |
FALSE |
C_CLKOUT15_FREQ |
0 |
C_CLKOUT15_PHASE |
0 |
C_CLKOUT15_GROUP |
NONE |
C_CLKOUT15_BUF |
TRUE |
C_CLKOUT15_VARIABLE_PHASE |
FALSE |
C_CLKFBIN_FREQ |
0 |
C_CLKFBIN_DESKEW |
NONE |
C_CLKFBOUT_FREQ |
0 |
C_CLKFBOUT_PHASE |
0 |
C_CLKFBOUT_GROUP |
NONE |
C_CLKFBOUT_BUF |
TRUE |
C_PSDONE_GROUP |
NONE |
C_EXT_RESET_HIGH |
0 |
C_CLK_PRIMITIVE_FEEDBACK_BUF |
FALSE |
C_CLKOUT0_DUTY_CYCLE |
0.500000 |
C_CLKOUT1_DUTY_CYCLE |
0.500000 |
C_CLKOUT2_DUTY_CYCLE |
0.500000 |
C_CLKOUT3_DUTY_CYCLE |
0.500000 |
C_CLKOUT4_DUTY_CYCLE |
0.500000 |
C_CLKOUT5_DUTY_CYCLE |
0.500000 |
C_CLKOUT6_DUTY_CYCLE |
0.500000 |
C_CLKOUT7_DUTY_CYCLE |
0.500000 |
C_CLKOUT8_DUTY_CYCLE |
0.500000 |
C_CLKOUT9_DUTY_CYCLE |
0.500000 |
C_CLKOUT10_DUTY_CYCLE |
0.500000 |
C_CLKOUT11_DUTY_CYCLE |
0.500000 |
C_CLKOUT12_DUTY_CYCLE |
0.500000 |
C_CLKOUT13_DUTY_CYCLE |
0.500000 |
C_CLKOUT14_DUTY_CYCLE |
0.500000 |
C_CLKOUT15_DUTY_CYCLE |
0.500000 |
C_CLK_GEN |
UPDATE |
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Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
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proc_sys_reset_0
Processor System Reset Module Reset management module
|
IP Specs |
Core |
Version |
Documentation |
proc_sys_reset |
3.00.a |
IP |
|
 |
PORT LIST |
These are the ports listed in the MHS file.
Please refer to the IP documentation for complete information about module ports.
|
# |
NAME |
DIR |
[LSB:MSB] |
SIGNAL |
0 |
Slowest_sync_clk |
I |
1 |
clk_50_0000MHz |
1 |
Ext_Reset_In |
I |
1 |
sys_rst_s |
2 |
MB_Debug_Sys_Rst |
I |
1 |
Debug_SYS_Rst |
3 |
Dcm_locked |
I |
1 |
Dcm_all_locked |
4 |
MB_Reset |
O |
1 |
mb_reset |
5 |
Bus_Struct_Reset |
O |
1 |
sys_bus_reset |
6 |
Peripheral_Reset |
O |
1 |
sys_periph_reset |
|
Parameters |
These are the current parameter settings for this module.
Parameters marked with
yellow
indicate parameters set by the user.
Parameters marked with
blue
indicate parameters set by the system.
|
Name |
Value |
C_SUBFAMILY |
lx |
C_EXT_RST_WIDTH |
4 |
C_AUX_RST_WIDTH |
4 |
C_EXT_RESET_HIGH |
0 |
C_AUX_RESET_HIGH |
1 |
C_NUM_BUS_RST |
1 |
C_NUM_PERP_RST |
1 |
C_NUM_INTERCONNECT_ARESETN |
1 |
C_NUM_PERP_ARESETN |
1 |
C_FAMILY |
virtex5 |
Post Synthesis Device Utilization |
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
|
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Post Synthesis Clock Limits |
No clocks could be identified in the design. Run platgen to generate synthesis information.
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