Required knowledge

• The measurement is based on the hardware description language, Verilog. Students should read and learn the basic concepts of this language, see the attached file "David Harris: Structural Design with Verilog".
• The students should be able to interpret the Verilog codes that will be used during the measurement (see the attached file: "Lab. guide, ISE tutorial, measurement tasks").

Downloading Xilinx ISE Webpack

From the university: ISE WebPACK 14.2
From the Xilinx webpage

Be sure to select Webpack during the install process, otherwise the software will work for a 30 day trial period.
A license file is required after the installation. You can generate it online at Xilinx website (registration required) or you can download a license file for ISE Webpack

An easier way to use Xilinx ISE Webpack can be found here

Using the following online tool, you can make a nice report with color source codes: http://www.mensus.net/widgets/color.shtml

Before the measurement, read the attached documents!

Known ISE bugs and work-arunds (v13.2)

Course materials

• Lab. guide, ISE tutorial, measurement tasks
• Verilog/FPGA presentation (zip)
• David Harris: Structural Design with Verilog